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2019-09-16 20:25:01 -0600 edited question 各型号Vref/VRP是怎么接的？

各型号Vref是怎么接的？ 各型号产品的Vref是怎么接的？我需要考虑使用sstl等电平

2019-09-16 20:24:22 -0600 asked a question 各型号Vref/VRP是怎么接的？

各型号Vref是怎么接的？ 各型号产品的Vref是怎么接的？

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2019-07-29 21:15:00 -0600 asked a question 没有xilinx的vivado license，你们可以提供？

没有xilinx的vivado license，你们可以提供？ 没有xilinx的vivado license，你们可以提供？

2019-07-12 03:19:17 -0600 answered a question MDM的setup有什么需要注意的？我们没跑起来

1）建议先把我们tutorial跑起来，点击这里下载： 这样，流程通了以后，就好办了； 2）然后自己工程里，建议先少量添加信号，走通全流程； 3）然后返回，添加更多信号。

2019-06-19 03:14:49 -0600 edited answer timing时序有问题，一般你们建议怎么做？

Timing closure(时序收敛)是很多人关心的而又似乎不能穷尽的问题。按照一张表做完，就达到努力最大化了： 1）综合阶段：Synplify的retiming可以在综合阶段最大化性能，可以尝试；不需要过约束； 2）时序约束阶
2019-06-19 03:14:25 -0600 edited answer timing时序有问题，一般你们建议怎么做？

Timing closure(时序收敛)是很多人关心的而又似乎不能穷尽的问题。按照一张表做完，就达到努力最大化了： 1）综合阶段：Synplify的retiming可以在综合阶段最大化性能，可以尝试；不需要过约束； 2）时序约束阶
2019-06-18 22:26:39 -0600 edited answer timing时序有问题，一般你们建议怎么做？

Timing closure(时序收敛)是很多人关心的而又似乎不能穷尽的问题。按照一张表做完，就达到努力最大化了： 1）综合阶段：Synplify的retiming可以在综合阶段最大化性能，可以尝试；不需要过约束； 2）时序约束阶
2019-06-18 22:21:34 -0600 answered a question timing时序有问题，一般你们建议怎么做？

Timing closure(时序收敛)是很多人关心的而又似乎不能穷尽的问题。按照一张表做完，就达到努力最大化了： 1）综合阶段：Synplify的retiming可以在综合阶段最大化性能，可以尝试；不需要过约束； 2）时序约束阶
2019-05-21 20:53:33 -0600 edited question 黑盒子是怎么处理的？

黑盒子是怎么处理的？ 黑盒子是怎么处理的？ xci、dcp、edf文件等用哪个？这三个文件区别是什么？

2019-05-21 20:51:31 -0600 asked a question 黑盒子是怎么处理的？

黑盒子是怎么处理的？ 黑盒子是怎么处理的？ xci、dcp、edf文件等用哪个？

2019-05-16 22:54:11 -0600 answered a question 你们板子可以用jtag线下载吗？需要什么设置吗？

可以。 不需要设置。直接连接上jtag口就行了。 注意jtag电缆的usb驱动问题，需要在“设备管理器”里面查看电缆是否被计算机正确识别。

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2019-05-13 20:58:56 -0600 asked a question 同样bit文件，下进去两块板不一样，是不是fpga坏了？

同样bit文件，下进去两块板不一样，是不是fpga坏了？ 同样bit文件，下进去两块板不一样，是不是fpga坏了？

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